Emerging physical unclonable functions with nanotechnology

Physical unclonable functions (PUFs) are increasingly used for authentication and identification applications as well as the cryptographic key generation. An important feature of a PUF is the reliance on minute random variations in the fabricated hardware to derive a trusted random key. Currently, most PUF designs focus on exploiting process variations intrinsic to the CMOS technology. In recent years, progress in emerging nanoelectronic devices has demonstrated an increase in variation as a consequence of scaling down to the nanoregion. To date, emerging PUFs with nanotechnology have not been fully established, but they are expected to emerge. Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs

Memristive crypto primitive for building highly secure physical unclonable functions

Physical unclonable functions (PUFs) exploit the intrinsic complexity and irreproducibility of physical systems to generate secret information. The advantage is that PUFs have the potential to provide fundamentally higher security than traditional cryptographic methods by preventing the cloning of devices and the extraction of secret keys. Most PUF designs focus on exploiting process variations in Complementary Metal Oxide Semiconductor (CMOS) technology. In recent years, progress in nanoelectronic devices such as memristors has demonstrated the prevalence of process variations in scaling electronics down to the nano region. In this paper, we exploit the extremely large information density available in nanocrossbar architectures and the significant resistance variations of memristors to develop an on-chip memristive device based strong PUF (mrSPUF). Our novel architecture demonstrates desirable characteristics of PUFs, including uniqueness, reliability, and large number of challenge-response pairs (CRPs) and desirable characteristics of strong PUFs. More significantly, in contrast to most existing PUFs, our PUF can act as a reconfigurable PUF (rPUF) without additional hardware and is of benefit to applications needing revocation or update of secure key information.Yansong Gao, Damith C. Ranasinghe, Said F. Al-Sarawi, Omid Kavehei, Derek Abbot

Emerging physical unclonable functions with nanotechnology

Physical unclonable functions (PUFs) are increasingly used for authentication and identification applications as well as the cryptographic key generation. An important feature of a PUF is the reliance on minute random variations in the fabricated hardware to derive a trusted random key. Currently, most PUF designs focus on exploiting process variations intrinsic to the CMOS technology. In recent years, progress in emerging nanoelectronic devices has demonstrated an increase in variation as a consequence of scaling down to the nanoregion. To date, emerging PUFs with nanotechnology have not been fully established, but they are expected to emerge. Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs

The Fourth Element: Characteristics, Modelling, and Electromagnetic Theory of the Memristor

In 2008, researchers at HP Labs published a paper in {\it Nature} reporting the realisation of a new basic circuit element that completes the missing link between charge and flux-linkage, which was postulated by Leon Chua in 1971. The HP memristor is based on a nanometer scale TiO$_2$ thin-film, containing a doped region and an undoped region. Further to proposed applications of memristors in artificial biological systems and nonvolatile RAM (NVRAM), they also enable reconfigurable nanoelectronics. Moreover, memristors provide new paradigms in application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). A significant reduction in area with an unprecedented memory capacity and device density are the potential advantages of memristors for Integrated Circuits (ICs). This work reviews the memristor and provides mathematical and SPICE models for memristors. Insight into the memristor device is given via recalling the quasi-static expansion of Maxwell's equations. We also review Chua's arguments based on electromagnetic theory.Comment: 28 pages, 14 figures, Accepted as a regular paper - the Proceedings of Royal Society

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes

Corrigendum: Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals.

Nature Communications 8: Article number: 14482; published: 17 February 2017; Updated: 22 March 2017 The original version of this Article contained a typographical error in the spelling of the author Omid Kavehei, which was incorrectly given as Omid Kevehei. This has now been corrected in both the PDF and HTML versions of the Article.</jats:p

Maximally redundant high-radix signed-digit adder: new algorithm and implementation

Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (SD) or generally High-Radix SD (HRSD) number system is one of the most important redundant number systems. HRSD additions are used in many arithmetic functions as basic operations. Hence, improving the additions characteristics will improve the performance of almost all arithmetic modules. Several HRSD adders have been introduced in literatures. In this paper a new maximally redundant HRSD adder is proposed. This adder is compared to some most efficient HRSD adders previously published. The proposed adder is fabricated using a standard TSMC 65nm CMOS technology at 1volt supply voltage. The adder consumes 2.5% less power than the best previous published HRSD design. These implementations are also synthesized with FPGA flow on Xilinx Virtex2. The experimental result shows 5% and 6% decreases in the area and delay, respectively

Ágora y la Biblioteca de Alejandría

Sección: ReseñasEn octubre se estrenaba “Ágora”, el quinto trabajo de Alejandro Amenábar con gran éxito de taquilla y críticas para todos los gustos. El director de “Mar adentro” ha cambiado radicalmente de género y nos ofrece un drama histórico al más puro estilo de las superproducciones de Hollywood, un péplum con muchos extras y espectaculares decorados que inevitablemente nos recuerda a Espartaco, Cleopatra o Ben Hur.N

High fill factor low-voltage CMOS image sensor based on time-to-threshold PWM VLSI architecture

This paper presents a CMOS image sensor (CIS) VLSI architecture based on a single-inverter time-tothreshold pulsewidth modulation circuitry capable of operating as low as 330-mV supply voltage while retaining a signal-to-noise ratio of 24 dB; an important characteristic being demanded by very low voltage portable CIS-based equipment such as disposable medical cameras and on-chip autonomous wireless security vision systems. A 64 × 64 pixel array was fabricated using standard 130-nm CMOS process consuming only 5.9 nW/pixel with integration time of 2 ms at +0.5 V supply. The high fill factor of 58% facilitated a better SNR at a low supply voltage when compared with other CIS architectures. The pixel has a dynamic range of 54 dB with 7.8 frame per second